1. Technical Field of the Invention
This invention pertains to modeling. More particularly, it pertains to physical modeling of electronic modules, including interconnection of chip and chip carrier.
2. Background Art
Typically there are several ways for modeling chip and chip carrier interconnection layouts.
One approach is to review a data base of all previously designed modules, and select the one with matching fundamental parameters, such as die size, laminate size, number of chip input/output. A problem with this approach is the difficulty of identifying and dealing with all of the parameters required.
Another approach is to build the design from the start. This is time consuming process that often results in discarding the design as the parameters change due to new requirements and/or design objectives.
A third approach is to layout or sketch the die and laminate manually. The problem with this approach, again, is the level of skill and experience required, the difficulty of identifying and dealing with all of the parameters required, and the difficulty of visually expressing and modifying the design.
There is, consequently, a need in the art for a method and system for providing a quick and visual representation of a complicated module design which takes into account all relevant parameters. Such is needed for early modeling a more complex process and would be useful for early design and quick modeling chip carriers, such as plastic ball grid array (PBGA), flip chip, or wirebond chip carriers.
It is an object of the invention to provide an improved system and method for simulating and graphically assessing the cost and feasibility of general and specific wiring design cases.
It is a further object of the invention to provide a system and method for simulating general and specific wiring design cases and quickly assess the simulated design graphically.
It is a further object of the invention to provide a system and method for assessing a simulated wiring design with respect to crossing, choking, signal runs, wiring channels and input/output.
It is a further object of the invention to provide a system and method for providing simulated design graphical data to a wiring design tool.
In accordance with the preferred embodiment of the invention, a system and method is provided for modeling and estimating substrate characteristics preliminary to preparing a detailed design. Input parameters include die size and substrate size and, optionally, a netlist of interconnections between the die and substrate. Responsive to these input parameters, a representation of an optimized estimated fanout of the interconnections is graphically presented together with a set of substrate parameters derived from the optimized estimated fanout.
In accordance with an aspect of the invention, there is provided a computer program product configured to be operable to graphically model an optimized fanout of die to substrate interconnections.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.